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rev 2.0, may 28, 2008 page 1 of 18 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax: (408) 855-0550 www.spectralinear.com sl23ep08 low jitter and skew 10 to 220 mhz zero dela y buffer ( zdb ) key features ? 10 to 220 mhz operating frequency range ? low output clock skew: 70ps-typ ? low output clock jitter: <200ps ? low part-to-part output skew: 150 ps-typ ? 3.3v to 2.5v power supply range ? low power dissipation: ? - 22 ma-typ at 66mhz and vdd=3.3v ? - 20 ma-typ at 66mhz and vdd=2.5v ? one input drives 8 outputs ? multiple configuration and drive options ? select mode to bypass pll or tri-state outputs ? spreadthru? pll that allows use of sscg ? available in 16-pin soic and tssop packages ? available in commercial and industrial grades applications ? printers, mfps and digital copiers ? pcs and work stations ? routers, switchers and servers ? datacom and telecom ? high-speed digital embeded systems description the sl23ep08 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to eight (8) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product has an on-chip pll and a feedback pin (fbk) which can be used to obtain feedback from any one of the output clocks. the sl23ep08 has two (2) clock driver banks each with four (4) clock outputs. these outputs are controlled by two (2) select input pins s1 and s2. when only four (4) outputs are needed, bank-b output clock buffers can be tri-stated to reduce power dissipation and jitter. the select inputs can also be used to tri-state both banks a and b or drive them directly from the input bypassing the pll and making the product behave like a non-zero delay buffer (nzdb). the sl23ep08 offers various x/2,1x, 2x and 4x frequency options at the output clocks. refer to the ?product configuration table? for the details. the sl23ep08-1h, -2h and 5h versions operates up to 220 mhz and sl23ep08-1, -2, -3 and -4 versions operate up to 133 mhz with cl=15pf output load. benefits ? up to eight (8) distribution of input clock ? standard and high-dirive levels to control impedance level, frequency range and emi ? low skew, jitter and power dissipation block diagram low power and low jitter pll mux input selection decoding logic vdd gnd 2 2 s2 s1 clkin fbk clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 /2 /2 /2 (divider for -3 and -4) (divider for -5h only) (divider for -2, -2h and -3)
rev 2.0, may 28, 2008 page 2 of 18 sl23ep08 pin configuration 16-pin soic/tssop pin description pin number pin name pin type pin description 1 clkin input reference frequency clock input. 5v tolerant input. weak pull-down (250k ?). 2 clka1 output buffered clock output, bank a. weak pull-down (250k ?). 3 clka2 output buffered clock output, bank a. weak pull-down (250k ?). 4 vdd power 3.3v to 2.5v power supply. 5 gnd power power ground. 6 clkb1 output buffered clock output, bank b. weak pull-down (250k ?). 7 clkb2 output buffered clock output, bank b. weak pull-down (250k ?). 8 s2 input select input, select pin s2. weak pull-up (250k ?). 9 s1 input select input, select pin s1. weak pull-up (250k ?). 10 clkb3 output buffered clock output, bank b. weak pull-down (250k ?). 11 clkb4 output buffered clock output, bank b. weak pull-down (250k ?). 12 gnd power power ground. 13 vdd power 3.3v to 2.5v power supply. 14 clka3 output buffered clock output, bank a. weak pull-down (250k ?). 15 clka4 output buffered clock output, bank a. weak pull-down (250k ?). 16 fbk output pll feedback input.
rev 2.0, may 28, 2008 page 3 of 18 sl23ep08 general description the sl23ep08 is a low skew, low jitter zero delay buffer with very low operating current. the product includes an on-chip high performance pll that locks into the input reference clock and produces eight (8) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to fbk pin used for internal pll feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to eight (8). input and output frequency range the input and output frequency range is the same for sl23ep08-1 and -1h versions. for sl23ep08-2, -2h - 3, -4 and -5h versions, the output frequency is 1/2x, 1x, 2x, or 4x of the clkin as given in the ?available sl23ep08 configurations? table 3. but, the frequency range depends on vdd, drive levels and output load (c l ) as given in the ?electrical specification? tables. if the input clock frequency is dc (from gnd to vdd), this is detected by an input frequency detection circuitry and all eight (8) clock outputs are forced to hi- z. the pll is shutdown to save power. in this shutdown state, the product draws less than 10 a supply current. spreadthru? feature if a spread spectrum clock (ssc) were to be used as an input reference clock, the sl23ep08 is designed to pass the modulated spread spectrum clock (ssc) signal from its reference input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency. select input control the sl23ep08 provides two (2) input select control pins called s1 and s2. this feature enables users to selects various states of output clock banks-a and bank-b, output source and pll shutdown features as shown in the table 2. the s1 (pin-9) and s2 (pin-8) inputs include 250 k ? weak pull-down resistors to gnd. pll bypass mode if the s2=1 and s1=0, the on-chip pll is shutdown and bypassed, and all the eight (8) output clocks of bank a and bank b are driven directly from the reference input clock. in this operation mode sl23ep08 works like a non-zdb fanout buffer. high and low-drive product options the sl23ep08 is offered with high drive ?-1h, -2h and - 5h? and standard drive ?-1, -2, -3 and -4? options. these drive options enable the users to control load levels, frequency range and emi control. refer to the ac electrical tables for the details. sl23ep08-5h is offered only with high drive option. sl23ep08-3 and -4 are offered only with standard drive option. skew and zero delay all outputs should drive the similar load to achieve output-to-output skew and input-to-output delay specifications given in the ac electrical tables. however, zero-delay between input and outputs can be adjusted by changing the loading of fbk pin relative to the banks a and b clocks since fbk is the feedback to the pll. power supply range (vdd) the sl23ep08 is designed to operate with from 3.3v to 2.5v vdd power supply range. an internal on-chip voltage regulator is used to provide pll constant power supply of 1.8v, leading to a consistent and stable pll electrical performance in terms of skew, jitter and power dissipation. the sl23ep08 i/o is powered by using vdd.
rev 2.0, may 28, 2008 page 4 of 18 sl23ep08 figure 1. clkin input to clka and clkb delay s2 s1 clock a1-a4 clock b1-b4 output source pll shutdown and bypass 0 0 tri-state tri-state pll yes 0 1 driven tri-state pll no 1 0 driven driven reference(clkin) yes 1 1 driven driven pll no table 2. select input decoding device feedback from bank-a frequency bank-b frequency sl23ep08-1 and 1h bank-a or bank-b reference reference sl23ep08-2 and -2h [1] bank-a reference reference/2 sl23ep08-2 and -2h [1] bank-b 2x reference reference sl23ep08-3 [1] bank-a 2xreference reference [2] sl23ep08-3 [1] bank-b 4xreference 2xreference sl23ep08-4 bank-a or bank-b 2x reference 2x reference sl23ep08-5h bank-a or bank-b reference/2 reference/2 table 3. available sl23ep08 configurations notes: 1. outputs are inverted on sl23ep08-2, -2h and -3 in pll bypass mode when s2=1 and s1=0. use sl23ep08-1 if non-inverting outputs are required. 2. output phase is random (0 or 180 with respect to i nput clock). use sl23ep08-2 if phase integrity is required.
rev 2.0, may 28, 2008 page 5 of 18 sl23ep08 absolute maximum ratings description condition min max unit supply voltage, vdd -0.5 4.6 v all inputs and outputs -0.5 vdd+0.5 v ambient operating temperature in operation, c-grade 0 70 c ambient operating temperature in operation, i-grade -40 85 c storage temperature no power is applied -65 150 c junction temperature in operation, power is applied - 125 c soldering temperature - 260 c esd rating (human body model) jedecc22-a114d -4000 4000 v esd rating (charge device model) jedecc22-c101c -1500 1500 v esd rating (machine model) jedecc22-a115d -200 200 v operating conditions (c-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15pf and ambient temperature range 0 to +70c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.97 3.3 3.63 v operating temperature ta ambient temperature 0 - 70 c input capacitance vih pins 1, 8, 9 and 16 - 5 7 pf output impedance r out -1 high drive (-1h, -2h, -5h) - 28 - ? output impedance r out -2 standard drive (-1, -2, -3, -4) - 40 - ?
rev 2.0, may 28, 2008 page 6 of 18 sl23ep08 dc electrical characteristics (c-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=1 5pf and ambient temperature range 0 to +70c description symbol condition min typ max unit input low voltage vinl clkin, s2 and s1 pins ? ? 0.8 v input high voltage vinh clkin, s2 and s1 pins 2.0 ? vdd+0.3 v input low current iinl 0 < vin < 0.8v clkin, s2 and s1 inputs ? 25 50 a input high current iinh vin = 2.4 to vdd clkin, s2 and s1 inputs ? ? 50 a iol = 8 ma (standard drive) ? ? 0.4 v output low voltage vol iol = 12 ma (high drive) ? ? 0.4 v ioh = ?8 ma (standard drive) 2.4 ? ? v output high voltage voh ioh = ?12 ma (high drive) 2.4 ? ? v power down supply current iiddpd measured at clkin= gnd to vdd or input is floating ? 8 12 a power supply current idd1 all outputs cl=0, 33.3 mhz clkin s2=s1=1 (high), all versions ? 16 20 ma power supply current idd2 all outputs cl=0, 66.6 mhz clkin s2=s1=1 (high), all versions ? 22 28 ma power supply current idd3 all outputs cl=0, 100 mhz clkin s2=s1=1 (high), all versions ? 28 36 ma power supply current idd4 all outputs cl=0, 133.3 mhz clkin s2=s1=1 (high), all versions ? 34 44 ma pull-up and pull-down resistors rpud pins-1/2/3/7/8/9/10/11/14/15 250k ? -typ 175 250 325 k ? switching electrical characteristics (c-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=1 5pf and ambient temperature range 0 to +70c description symbol condition min typ max unit fout1 cl=15pf, -1h and -2h 10 - 220 mhz fout2 cl=22pf, -1h and -2h 10 - 180 mhz fout3 cl=30pf, -1h and -2h 10 - 135 mhz fout4 cl=15pf, -1, -2, -3 and -4 10 - 180 mhz fout5 cl=22pf, -1, -2, -3 and -4 10 - 135 mhz output frequency range fout6 cl=30pf, -1, -2, -3 and -4 10 - 100 mhz input duty cycle dc1 measured at vdd/2, all versions 30 50 70 % output duty cycle dc2 cl=30pf, fout=66 mhz, all versions measured at vdd/2 40 50 60 %
rev 2.0, may 28, 2008 page 7 of 18 sl23ep08 output duty cycle dc3 cl=15pf, fout=66 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc4 cl=15pf, fout=133 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc5 cl=15pf, fout=166 mhz, all versions measured at vdd/2 45 50 55 % output rise/fall time tr/f1 cl=30pf, -1, -2, -3 and -4 versions 0.8v to 2.0v - - 2.2 ns output rise/fall time tr/f2 cl=15pf, -1, -2, -3 and -4 versions 0.8v to 2.0v - - 1.5 ns output rise/fall time tr/f3 cl=30pf, -1h and -2h and versions 0.8v to 2.0v - - 1.5 ns output rise/fall time tr/f4 cl=15pf, -1h and -2h and versions 0.8v to 2.0v - - 1.2 ns output-to-output skew on same bank skw2 -1 and -2, measured from 0.8v to 2.0v, and outputs are equally loaded - 80 170 ps output-to-output skew on same bank skw2 -1h and -2h and -4, measured at vdd/2 and outputs are equally loaded - 70 150 ps output-to-output skew between bank a and b skw3 -1, -1h, 2h and -4, measured at vdd/2 and outputs are equally loaded - 80 150 ps output-to-output skew between bank a and b skw4 -2, measured at vdd/2 and outputs are equally loaded - 130 300 ps device-to-device skew skw5 all versions, measured at vdd/2 and outputs are equally loaded - 150 400 ps input-to-output delay dt all versions, clkin to fbk rising edge, measured at vdd/2 and outputs are equally loaded and s2=s1=1 -200 - 200 ps fout=33 to 200mhz and cl=15pf - - 100 ps cycle-to-cycle jitter (-1 and -1h versions) ccj1 fout=33 to 200 mhz and cl=30pf - - 150 ps fout=66 mhz and cl=15pf - - 200 ps fout=66mhz and cl=30pf - - 200 ps cycle-to-cycle jitter (-4 and -5 versions) ccj2 fout=166mhz and cl=15pf - - 200 ps fout=66 mhz and cl=15pf - - 400 ps fout=133mhz and cl=30pf - - 400 ps cycle-to-cycle jitter (-2, -2h and -3 versions) ccj3 fout=166mhz and cl=15pf - - 400 ps pll lock time tlock from 0.95vdd and valid clock presented at clkin - - 1.0 ms
rev 2.0, may 28, 2008 page 8 of 18 sl23ep08 operating conditions (i-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=1 5pf and ambient temperature range -40 to +85c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.97 3.3 3.63 v operating temperature ta ambient temperature -40 - 85 c input capacitance vih pins 1, 8, 9 and 16 - 5 8 pf output impedance r out -1 high drive (-1h, -2h, -5h) - 28 - ? output impedance r out -2 standard drive (-1, -2, -3, -4) - 40 - ? dc electrical characteristics (i-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15pf and ambient temperature range -40 to +85 description symbol condition min typ max unit input low voltage vinl clkin, s2 and s1 pins ? ? 0.8 v input high voltage vinh clkin, s2 and s1 pins 2.0 ? vdd+0.3 v input low current iinl 0 < vin < 0.8v clkin, s2 and s1 inputs ? 25 50 a input high current iinh vin = 2.4 to vdd clkin, s2 and s1 inputs ? ? 50 a iol = 8 ma (standard drive) ? ? 0.4 v output low voltage vol iol = 12 ma (high drive) ? ? 0.4 v ioh = ?8 ma (standard drive) 2.4 ? ? v output high voltage voh ioh = ?12 ma (high drive) 2.4 ? ? v power down supply current iiddpd measured at clkin= gnd to vdd or input is floating ? 12 18 a power supply current idd1 all outputs cl=0, 33.3 mhz clkin s2=s1=1 (high), all versions ? 17 22 ma power supply current idd2 all outputs cl=0, 66.6 mhz clkin s2=s1=1 (high), all versions ? 24 32 ma power supply current idd3 all outputs cl=0, 100 mhz clkin s2=s1=1 (high), all versions ? 30 40 ma power supply current idd4 all outputs cl=0, 133.3 mhz clkin s2=s1=1 (high), all versions ? 38 50 ma pull-up and pull-down resistors rpud pins-1/2/3/7/8/9/10/11/14/15 250k ? -typ 125 250 375 k ?
rev 2.0, may 28, 2008 page 9 of 18 sl23ep08 switching electrical characteristics (i-grade) unless otherwise stated vdd= 3.3+/- 10%, cl=1 5pf and ambient temperature range -40 to +85c description symbol condition min typ max unit fout1 cl=15pf, -1h and -2h versions 10 - 220 mhz fout2 cl=22pf, -1h and -2h versions 10 - 180 mhz fout3 cl=30pf, -1h and -2h versions 10 - 135 mhz fout4 cl=15pf, -1, -2, -3 and -4 versions 10 - 180 mhz fout5 cl=22pf, -1, -2, -3 and -4 versions 10 - 135 mhz output frequency range fout6 cl=30pf, -1, -2, -3 and -4 versions 10 - 100 mhz input duty cycle dc1 measured at vdd/2, all versions 30 50 70 % output duty cycle dc2 cl=30pf, fout=66 mhz, all versions 40 50 60 % output duty cycle dc3 cl=15pf, fout=66 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc4 cl=15pf, fout=133 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc5 cl=15pf, fout=166 mhz, all versions measured at vdd/2 45 50 55 % output rise/fall time tr/f1 cl=30pf, -1, -2, -3 and -4 versions 0.8v to 2.0v - - 2.2 ns output rise/fall time tr/f2 cl=15pf, -1, -2, -3 and -4 versions 0.8 to 2.0v - - 1.5 ns output rise/fall time tr/f3 cl=30pf, -1h and -2h and versions 0.8v to 2.0v - - 1.5 ns output rise/fall time tr/f4 cl=15pf, -1h and -2h and versions 0.8v to 2.0v - - 1.2 ns output-to-output skew on same bank skw2 -1 and -2, measured from 0.8v to 2.0v, and outputs are equally loaded - 80 170 ps output-to-output skew on same bank skw2 -1h and -2h and -4, measured at vdd/2 and outputs are equally loaded - 70 150 ps output-to-output skew between bank a and b skw3 -1, -1h, 2h and -4, measured at vdd/2 and outputs are equally loaded - 80 150 ps output-to-output skew between bank a and b skw4 -2, measured at vdd/2 and outputs are equally loaded - 130 300 ps device-to-device skew skw5 all versions, measured at vdd/2 and outputs are equally loaded - 250 500 ps input-to-output delay dt all versions, clkin to fbk rising edge, measured at vdd/2 and outputs are equally loaded and s2=s1=1 -200 - 200 ps
rev 2.0, may 28, 2008 page 10 of 18 sl23ep08 fout=33 to 200mhz and cl=15pf - - 100 ps cycle-to-cycle jitter (-1 and -1h versions) ccj1 fout=33 to 200 mhz and cl=30pf - - 150 ps fout=66 mhz and cl=15pf - - 200 ps fout=66mhz and cl=30pf - - 200 ps cycle-to-cycle jitter (-4 and -5 versions) ccj2 fout=166mhz and cl=15pf - - 200 ps fout=66 mhz and cl=15pf - - 400 ps fout=133mhz and cl=30pf - - 400 ps cycle-to-cycle jitter (-2, -2h and -3 versions) ccj3 fout=166mhz and cl=15pf - - 400 ps pll lock time tlock from 0.95vdd and valid clkin - - 1.0 ms operating conditions (c-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15pf and ambient temperature range 0 to +70c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.25 2.5 2.75 v operating temperature ta ambient temperature 0 - 70 c input capacitance vih pins 1, 8, 9 and 16 - 5 7 pf output impedance r out -1 high drive (-1h, -2h, -5h) - 32 - ? output impedance r out -2 standard drive (-1, -2, -3, -4) - 41 - ?
rev 2.0, may 28, 2008 page 11 of 18 sl23ep08 dc electrical characteristics (c-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=1 5pf and ambient temperature range 0 to +70c description symbol condition min typ max unit input low voltage vinl clkin, s2 and s1 pins ? ? 0.7 v input high voltage vinh clkin, s2 and s1 pins 1.7 ? vdd+0.3 v 0 < vin < 0.7v clkin, s2 and s1 inputs ? 25 50 input low current iinl a vin = 1.7 to vdd clkin, s2 and s1 inputs ? ? 50 input high current iinh a iol = 6 ma (standard drive) ? ? 0.3 v output low voltage vol iol = 8 ma (high drive) ? ? 0.3 v ioh = ? 6 ma (standard drive) 2.0 ? ? v output high voltage voh ioh = ? 8 ma (high drive) 2.0 ? ? v power down supply current iiddpd measured at clkin= gnd to vdd or input is floating ? 8 12 a all outputs cl=0, 33.3 mhz clkin s2=s1=1 (high), all versions ? 15 18 power supply current idd1 ma all outputs cl=0, 66.6 mhz clkin s2=s1=1 (high), all versions ? 20 25 power supply current idd2 ma all outputs cl=0, 100 mhz clkin s2=s1=1 (high), all versions ? 26 33 power supply current idd3 ma all outputs cl=0, 133.3 mhz clkin s2=s1=1 (high), all versions ? 32 40 ma power supply current idd4 pins-1/2/3/7/8/9/10/11/14/15 250k ? -typ 125 250 375 pull-up and pull-down resistors rpud k ? switching electrical characteristics (c-grade) unless otherwise stated vdd= 2.5+/- 10%, cl=1 5pf and ambient temperature range 0 to +70c description symbol condition min typ max unit fout1 cl=15pf, -1h and -2h 10 - 170 mhz fout2 cl=22pf, -1h and -2h 10 - 135 mhz fout1 cl=30pf, -1h and -2h 10 - 100 mhz fout4 cl=15pf, -1, -2, -3 and -4 10 - 135 mhz output frequency range fout5 cl=22pf, -1, -2, -3 and -4 10 - 100 mhz fout1 cl=30pf, -1, -2, -3 and -4 10 - 75 mhz input duty cycle dc1 measured at vdd/2, all versions 30 50 70 %
rev 2.0, may 28, 2008 page 12 of 18 sl23ep08 output duty cycle dc2 cl=15pf, fout=66 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc3 cl=15pf, fout=133 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc4 cl=15pf, fout=166 mhz, all versions measured at vdd/2 40 50 60 % output rise/fall time tr/f1 cl=30pf, -1, -2, -3 and -4 versions measured at 0.6 to 1.8v - - 3.0 ns output rise/fall time tr/f2 cl=15pf, -1, -2, -3 and -4 versions measured at 0.6 to 1.8v - - 2.0 ns output rise/fall time tr/f3 cl=30pf, -1h and -2h and versions measured at 0.6 to 1.8v - - 1.4 ns output rise/fall time tr/f4 cl=15pf, -1h and -2h and versions measured at 0.6 to 1.8v - - 1.1 ns output-to-output skew on same bank skw2 -1 and -2, measured from 0.8v to 2.0v, and outputs are equally loaded - 80 200 ps output-to-output skew on same bank skw2 -1h and -2h and -4, measured at vdd/2 and outputs are equally loaded - 70 200 ps output-to-output skew between bank a and b skw3 -1, -1h, 2h and -4, measured at vdd/2 and outputs are equally loaded - 80 200 ps output-to-output skew between bank a and b skw4 -2, measured at vdd/2 and outputs are equally loaded - 130 350 ps device-to-device skew skw5 all versions, measured at vdd/2 and outputs are equally loaded - 150 500 ps input-to-output delay dt all versions, clkin to fbk rising edge, measured at vdd/2 and outputs are equally loaded and s2=s1=1 -250 - 250 ps fout=66 mhz and cl=15pf - - 200 ps cycle-to-cycle jitter (-1, -1h, -4 and -5 versions) ccj1 fout=133mhz and cl=15pf - - 200 ps fout=66mhz and cl=15pf - - 400 ps cycle-to-cycle jitter (-2, -2h and -3 versions) ccj2 fout=166mhz and cl=15pf - - 400 ps pll lock time tlock from 0.95vdd and valid clock presented at clkin - - 1.0 ms operating conditions (i-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=1 5pf and ambient temperature range -40 to +85c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.25 2.5 2.75 v operating temperature ta ambient temperature -40 - 85 c
rev 2.0, may 28, 2008 page 13 of 18 sl23ep08 input capacitance vih pins 1, 8, 9 and 16 - 5 8 pf output impedance r out -1 high drive (-1h, -2h, -5h) - 36 - ? output impedance r out -2 standard drive (-1, -2, -3, -4) - 42 - ? dc electrical characteristics (i-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15pf and ambient temperature range -40 to +85 description symbol condition min typ max unit input low voltage vinl clkin, s2 and s1 pins ? ? 0.7 v input high voltage vinh clkin, s2 and s1 pins 1.7 ? vdd+0.3 v 0 < vin < 0.7v clkin, s2 and s1 inputs ? 25 50 input low current iinl a vin = 1.7v to vdd clkin, s2 and s1 inputs ? ? 50 a input high current iinh iol = 6 ma (standard drive) ? ? 0.3 v output low voltage vol iol = 8 ma (high drive) ? ? 0.3 v ioh = ?6 ma (standard drive) 2.0 ? ? v output high voltage voh ioh = ?8 ma (high drive) 2.0 ? ? v power down supply current iiddpd measured at clkin= gnd to vdd or input is floating ? 8 12 a all outputs cl=0, 33.3 mhz clkin s2=s1=1 (high), all versions ? 16 20 power supply current idd1 ma all outputs cl=0, 66.6 mhz clkin s2=s1=1 (high), all versions ? 21 28 power supply current idd2 ma all outputs cl=0, 100 mhz clkin s2=s1=1 (high), all versions ? 27 36 ma power supply current idd3 all outputs cl=0, 133.3 mhz clkin s2=s1=1 (high), all versions ? 34 44 power supply current idd4 ma pins-1/2/3/7/8/9/10/11/14/15 250k ? -typ 125 250 375 pull-up and pull-down resistors rpud k ?
rev 2.0, may 28, 2008 page 14 of 18 sl23ep08 switching electrical characteristics (i-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15pf and ambient temperature range -40 to +85c description symbol condition min typ max unit fout1 cl=15pf, -1h and -2h versions 10 - 170 mhz fout2 cl=22pf, -1h and -2h versions 10 - 135 mhz fou3 cl=30pf, -1h and -2h versions 10 - 100 mhz fout4 cl=15pf, -1, -2, -3 and -4 versions 10 - 135 mhz fout5 cl=22pf, -1, -2, -3 and -4 versions 10 - 100 mhz output frequency range fout6 cl=30pf, -1, -2, -3 and -4 versions 10 - 75 mhz input duty cycle dc1 measured at vdd/2, all versions 30 50 70 % output duty cycle dc2 cl=15pf, fout=66 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc3 cl=15pf, fout=133 mhz, all versions measured at vdd/2 45 50 55 % output duty cycle dc4 cl=15pf, fout=166 mhz, all versions measured at vdd/2 40 50 60 % output rise/fall time tr/f1 cl=30pf, -1, -2, -3 and -4 versions measured at 0.6 to 1.8v - - 3.0 ns output rise/fall time tr/f2 cl=15pf, -1, -2, -3 and -4 versions measured at 0.6 to 1.8v - - 2.0 ns output rise/fall time tr/f3 cl=30pf, -1h and -2h and versions measured at 0.6 to 1.8v - - 1.5 ns output rise/fall time tr/f4 cl=15pf, -1h and -2h and versions measured at 0.6 to 1.8v - - 1.2 ns output-to-output skew on same bank skw2 -1 and -2, measured from 0.8v to 2.0v, and outputs are equally loaded - 100 220 ps output-to-output skew on same bank skw2 -1h and -2h and -4, measured at vdd/2 and outputs are equally loaded - 100 220 ps output-to-output skew between bank a and b skw3 -1, -1h, 2h and -4, measured at vdd/2 and outputs are equally loaded - 100 220 ps output-to-output skew between bank a and b skw4 -2, measured at vdd/2 and outputs are equally loaded - 180 375 ps device-to-device skew skw5 all versions, measured at vdd/2 and outputs are equally loaded - 275 550 ps input-to-output delay dt all versions, clkin to fbk rising edge, measured at vdd/2 and outputs are equally loaded and s2=s1=1 -200 - 200 ps fout=66 mhz and cl=15pf - - 200 ps cycle-to-cycle jitter (-1, -1h, -4 and -5 versions) ccj1 fout=133mhz and cl=15pf - - 200 ps cycle-to-cycle jitter ccj2 fout=66 mhz and cl=15pf - - 400 ps
rev 2.0, may 28, 2008 page 15 of 18 sl23ep08 (-2, -2h and -3 versions) fout=166mhz and cl=15pf - - 400 ps pll lock time tlock from 0.95vdd and valid clkin - - 1.0 ms external components & design considerations typical application schematic comments and recommendations decoupling capacitor: a minimum decoupling capacitor of 0.1 f must be used between vdd and vss pins. additional capacitors may be necessary depending on the application. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor: a series termination resistor is recommended if the distance between the output clocks and the load is over 1 ? inch. the nominal impedance of the clock outputs is given on the operating conditions tables. place the series termination resistors as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achieve ?zero delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on-chip for feedback to pll. for applications requiring zero input/output delay, the load at the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between bank a and b clocks and clkin. for minimum pin-to-pin skew, the external load at all the bank a and b clocks must be the same.
rev 2.0, may 28, 2008 page 16 of 18 sl23ep08 package outline and package dimensions 16-lead tssop (4.4-mm) 0.190(0.007) 0.300(0.012) 0.090(0.003) 0.200(0.008) 8 9 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 4.900(0.193) 5.100(0.200) 0.800(0.031) 1.050(0.041) 0.050(0.002) 0.150(0.006) 1.200(0.047) max 0.076(0.003) 0 to 8 0.500(0.020) 0.750(0.030) 0.250(0.010) bsc gauge plane dimensions are in milimeters (inches) top line: (min) and bottom line: (max) pin-1 id seating plane 1 16 0.650(0.025) bsc thermal characteristics parameter symbol condition min typ max unit ja still air - 105 - c/w ja 1m/s air flow - 95 - c/w thermal resistance junction to ambient ja 3m/s air flow - 90 - c/w thermal resistance junction to case jc independent of air flow - 35 - c/w
rev 2.0, may 28, 2008 page 17 of 18 sl23ep08 package drawing and dimensions (cont.) thermal characteristics parameter symbol condition min typ max unit ja still air - 80 - c/w ja 1m/s air flow - 74 - c/w thermal resistance junction to ambient ja 3m/s air flow - 71 - c/w thermal resistance junction to case jc independent of air flow - 44 - c/w
rev 2.0, may 28, 2008 page 18 of 18 sl23ep08 ordering information [3] ordering number marking shipping package package temperature sl23ep08sc-1 sl23ep08sc-1 tube 16-pin soic 0 to 70c sl23ep08sc-1t sl23ep08sc-1 tape and reel 16-pin soic 0 to 70c sl23ep08si-1 sl23ep08si-1 t ube 16-pin soic -40 to 85c sl23ep08si-1t sl23ep08si-1 tape and reel 16-pin soic -40 to 85c sl23ep08sc-1h sl23ep08sc-1h tube 16-pin soic 0 to 70c sl23ep08sc-1ht sl23ep08sc-1h tape and reel 16-pin soic 0 to 70c sl23ep08si-1h sl23ep08si-1h tube 16-pin soic -40 to 85c sl23ep08si-1ht sl23ep08si-1h tape and reel 16-pin soic -40 to 85c sl23ep08zc-1 sl23ep08zc-1 tube 16-pin tssop 0 to 70c sl23ep08zc-1t sl23ep08zc-1 tape and reel 16-pin tssop 0 to 70c sl23ep08zi-1 sl23ep08zi-1 tube 16-pin tssop -40 to 85c sl23ep08zi-1t sl23ep08zi-1 tape and reel 16-pin tssop -40 to 85c sl23ep08zc-1h sl23ep08zc-1h tube 16-pin tssop 0 to 70c sl23ep08zc-1ht sl23ep08zc-1h tape and reel 16-pin tssop 0 to 70c sl23ep08zi-1h sl23ep08zi-1h tube 16-pin tssop -40 to 85c sl23ep08zi-1ht sl23ep08zi-1h tape and reel 16-pin tssop -40 to 85c sl23ep08sc-2 sl23ep08sc-2 tube 16-pin soic 0 to 70c SL23EP08SC-2T sl23ep08sc-2 tape and reel 16-pin soic 0 to 70c sl23ep08si-2 sl23ep08si-2 t ube 16-pin soic -40 to 85c sl23ep08si-2t sl23ep08si-2 tape and reel 16-pin soic -40 to 85c sl23ep08sc-2h sl23ep08sc-2h tube 16-pin soic 0 to 70c sl23ep08sc-2ht sl23ep08sc-2h tape and reel 16-pin soic 0 to 70c sl23ep08sc-3 sl23ep08sc-3 tube 16-pin soic 0 to 70c sl23ep08sc-3t sl23ep08sc-3 tape and reel 16-pin soic 0 to 70c sl23ep08si-3 sl23ep08si-3 t ube 16-pin soic -40 to 85c sl23ep08si-3t sl23ep08si-3 tape and reel 16-pin soic -40 to 85c sl23ep08sc-4 sl23ep08sc-4 tube 16-pin soic 0 to 70c sl23ep08sc-4t sl23ep08sc-4 tape and reel 16-pin soic 0 to 70c sl23ep08si-4 sl23ep08si-4 t ube 16-pin soic -40 to 85c sl23ep08si-4t sl23ep08si-4 tape and reel 16-pin soic -40 to 85c sl23ep08sc-5h sl23ep08sc-5h tube 16-pin soic 0 to 70c sl23ep08sc-5ht sl23ep08sc-5h tube 16-pin soic 0 to 70c notes: 3. the sl23ep08 products are rohs compliant. while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. thi s product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperat ure range, high reliability, or any other extraordinary enviro nmental requirements unless pursuant to additional processing by spectra linear inc., and an expressed written agreement by spectra linear inc. spectra linear inc. reserves the right to change any circuitry or specification without notice.

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